1. Field of the Invention
Embodiments of the invention relate to memory devices, and more particularly, in one or more embodiments, to flash memory devices.
2. Description of the Related Art
Flash memory devices are non-volatile memory devices which store information on a semiconductor in a way that needs no power to maintain the information stored therein. Flash memory devices have been widely used as mass-storage devices because of their high storage densities and low costs.
Referring to FIG. 1, a conventional NAND flash memory device is arranged in a plurality of memory blocks. The plurality of memory blocks 10 includes first to N-th memory blocks 100. Each of the memory blocks 100 includes a plurality of memory cells typically arranged in a matrix form.
FIG. 2A illustrates a memory block 100. The illustrated memory block 100 includes first to m-th bit lines BL0-BLm and first to n-th word lines WL0-WLn. In some arrangements, m can be 32,767 or 65,535, and n can be 32 or 64. The bit lines BL0-BLm extend parallel to one another in a column direction. The word lines WL0-WLn extend parallel to one another in a row direction perpendicular to the column direction. The memory block 100 also includes upper and lower bit line select transistors 120a, 120b for selecting one or more bit lines in the memory block 100.
Each bit line includes a string of memory cells 110. For example, the second bit line BL1 includes memory cells 110 connected in series. Each of the memory cells 110 includes a floating gate transistor. The floating gate transistors of a bit line are coupled to one another in series from source to drain. The control gates of the floating gate transistors of memory cells 110 of a common row are coupled to the same word line. Each of the memory cells 110 stores a charge (or a lack of charge). The amount of stored charge can be used to represent, for example, one or more states, which can represent one or more digits (for example, bits) of data. The charge stored in the floating gate transistor sets the threshold voltage of the floating gate transistor. The memory cells 110 can be either a single-level cell (SLC) or a multi-level cell (MLC). In one arrangement, the amounts of charge stored in the memory cells 110 may be detected by sensing currents flowing through the floating gate transistors of the memory cells 110. In another arrangement, the amounts of charge stored in the memory cells 110 may be detected by sensing the threshold voltage values of the floating gate transistors of the memory cells 110.
FIG. 2B illustrates a cross-section of the floating gate transistors of the memory cells 110 in the second bit line BL1. The floating gate transistors are formed on a substrate 201. Each of the floating gate transistors includes a source region 210 (which can be a drain region for a neighboring transistor of the same bit line), a drain region 212 (which can be a source region for a neighboring transistor of the same bit line), a doped channel region 214, a first dielectric 216 (for example, a tunnel oxide), a floating gate 218, a second dielectric 220 (for example, a gate oxide, wherein the tunnel and gate oxide can be formed of the same or different material), and a control gate 222. The first dielectric 216 is formed on the channel region 214 to insulate the floating gate 218 from the channel region 214. The second dielectric 220 physically and electrically separates the floating gate 218 from the control gate 222. The control gate 222 is coupled to an appropriate word line, for example, word line WL1. Electrons can be trapped on the floating gate 218 and be used to store data.
Referring now to FIG. 2C, a conventional method of writing data on a memory block will be described. FIG. 2C schematically illustrates the memory block 100 of FIG. 2A, and only shows memory cells 110, bit lines BL0-BLm, and word lines WL0-WLn. However, it will be understood that the memory block 100 can include other components as described earlier in connection with FIGS. 2A and 2B.
During a write operation, data is typically written on a set of memory cells coupled to a single word line. Such a set of memory cells can be referred to as a “page.” In one arrangement, a page may include all memory cells sharing a word line. In other arrangements, a page may be formed by every two memory cells coupled to a single word line. In certain arrangements, a page may be formed by every four memory cells coupled to a single word line. It will be understood that a page may be formed by any suitable selected number of memory cells coupled to a word line.